if (imm.pp) {
ipsr->pp = 1;
psr.pp = 1; // priv perf ctrs always enabled
-// FIXME: need new field in mapped_regs_t for virtual psr.pp (psr.be too?)
- PSCB(vcpu,tmp[8]) = 0; // but fool the domain if it gets psr
+ PSCB(vcpu,vpsr_pp) = 0; // but fool the domain if it gets psr
}
if (imm.up) { ipsr->up = 0; psr.up = 0; }
if (imm.sp) { ipsr->sp = 0; psr.sp = 0; }
if (imm.dfh) ipsr->dfh = 1;
if (imm.dfl) ipsr->dfl = 1;
if (imm.pp) {
- ipsr->pp = 1; psr.pp = 1;
-// FIXME: need new field in mapped_regs_t for virtual psr.pp (psr.be too?)
- PSCB(vcpu,tmp[8]) = 1;
+ ipsr->pp = 1;
+ psr.pp = 1;
+ PSCB(vcpu,vpsr_pp) = 1;
}
if (imm.sp) { ipsr->sp = 1; psr.sp = 1; }
if (imm.i) {
if (newpsr.dfl) ipsr->dfl = 1;
if (newpsr.pp) {
ipsr->pp = 1; psr.pp = 1;
-// FIXME: need new field in mapped_regs_t for virtual psr.pp (psr.be too?)
- PSCB(vcpu,tmp[8]) = 1;
+ PSCB(vcpu,vpsr_pp) = 1;
}
else {
ipsr->pp = 1; psr.pp = 1;
- PSCB(vcpu,tmp[8]) = 0;
+ PSCB(vcpu,vpsr_pp) = 0;
}
if (newpsr.up) { ipsr->up = 1; psr.up = 1; }
if (newpsr.sp) { ipsr->sp = 1; psr.sp = 1; }
else newpsr.ic = 0;
if (PSCB(vcpu,metaphysical_mode)) newpsr.dt = 0;
else newpsr.dt = 1;
-// FIXME: need new field in mapped_regs_t for virtual psr.pp (psr.be too?)
- if (PSCB(vcpu,tmp[8])) newpsr.pp = 1;
+ if (PSCB(vcpu,vpsr_pp)) newpsr.pp = 1;
else newpsr.pp = 0;
*pval = *(unsigned long *)&newpsr;
return IA64_NO_FAULT;
unsigned long interrupt_mask_addr;
int pending_interruption;
int incomplete_regframe; // see SDM vol2 6.8
- unsigned long reserved5_1[4];
+ unsigned char vpsr_pp;
+ unsigned char reserved5_2[7];
+ unsigned long reserved5_1[3];
int metaphysical_mode; // 1 = use metaphys mapping, 0 = use virtual
int banknum; // 0 or 1, which virtual register bank is active
unsigned long rrs[8]; // region registers
unsigned long krs[8]; // kernel registers
unsigned long pkrs[8]; // protection key registers
unsigned long tmp[8]; // temp registers (e.g. for hyperprivops)
- // FIXME: tmp[8] temp'ly being used for virtual psr.pp
};
};
unsigned long reserved6[3456];